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DATE
2007
IEEE
79views Hardware» more  DATE 2007»
13 years 11 months ago
Utilization of SECDED for soft error and variation-induced defect tolerance in caches
Combination of SECDED with a redundancy technique can effectively tolerate a high variation-induced defect rate in future processes. However, while a defective cell in a block can...
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima,...
PRDC
2006
IEEE
13 years 11 months ago
SEVA: A Soft-Error- and Variation-Aware Cache Architecture
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
13 years 9 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer