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» VHDL switch level fault simulation
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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 8 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
13 years 8 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
13 years 9 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
ASIAMS
2007
IEEE
13 years 10 months ago
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks
Simulation is perhaps the most cost-effective tool to evaluate the operation of a system under design. A flexible, easy to extend, fully object-oriented, and multilayered simulato...
Abbas Nayebi, Sina Meraji, Arash Shamaei, Hamid Sa...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
13 years 9 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...