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EURODAC
1995
IEEE
159views VHDL» more  EURODAC 1995»
10 years 6 months ago
Timing constraint specification and synthesis in behavioral VHDL
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
10 years 6 months ago
Logic and Fault Simulation by Cellular Automata
Yih-Lang Li, Cheng-Wen Wu
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