4 search results - page 1 / 1 » VL-CDRAM: variable line sized cached DRAMs |
CODES
2003
IEEE
13 years 10 months ago
2003
IEEE
VTS
2011
IEEE
12 years 9 months ago
2011
IEEE
This paper proposes an adaptive multi-bit error correcting code for phase change memories that provides a manifold increase in the lifetime of phase change memories thereby making...
EUROPDS
1997
13 years 6 months ago
1997
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
HPCA
2012
IEEE
12 years 24 days ago
2012
IEEE
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond...