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ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
VLSISP
2008
147views more  VLSISP 2008»
13 years 3 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
ASAP
2003
IEEE
113views Hardware» more  ASAP 2003»
13 years 9 months ago
A VLSI Architecture for Advanced Video Coding Motion Estimation
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in area of variable block searching motion est...
Swee Yeow, John V. McCanny
APCCAS
2006
IEEE
241views Hardware» more  APCCAS 2006»
13 years 6 months ago
A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding
The paper presents a hardware friendly fast algorithm and its architecture for motion estimation (ME) in H.264 video coding. The fast algorithm adopts the quarter pel subsampling a...
Chia-Chun Lin, Yu-Kun Lin, Tian-Sheuan Chang
VLSISP
2008
132views more  VLSISP 2008»
13 years 4 months ago
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames f...
Brian M. H. Li, Philip Heng Wai Leong