25 search results - page 5 / 5 » VLSI Layout of Benes Networks |
ISVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
SOFSEM
2005
Springer
13 years 10 months ago
2005
Springer
d Abstract) Lubomir Torok Institute of Mathematics and Computer Science Slovak Academy of Sciences Severna 5, 974 01 Banska Bystrica, Slovak Republic 3-dimensional layout of graph...
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
The dual-cube is a newly proposed topology for interconnection networks, which uses low dimensional hypercubes as building blocks. The primary advantages of the dual-cube over the...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear sc...
MST
2002
13 years 5 months ago
2002
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...