22 search results - page 1 / 5 » Variable Partitioning and Scheduling of Multiple Memory Arch... |
IPPS
2002
IEEE
13 years 9 months ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
ISCAS
2002
IEEE
13 years 9 months ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
ICASSP
2008
IEEE
13 years 10 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
ASPDAC
2001
ACM
13 years 7 months ago
2001
ACM
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...