Sciweavers

29 search results - page 1 / 6
» Variable Resizing for Area Improvement in Behavioral Synthes...
Sort
View
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 4 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
DAC
1998
ACM
13 years 8 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
ASPDAC
2008
ACM
87views Hardware» more  ASPDAC 2008»
13 years 6 months ago
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...
Tsuyoshi Sadakata, Yusuke Matsunaga
DAC
1997
ACM
13 years 8 months ago
An Improved Algorithm for Minimum-Area Retiming
The concept of improving the timing behavior of a circuit by relocating flip-flops is called retiming and was first presented by Leiserson and Saxe. The ASTRA algorithm propose...
Naresh Maheshwari, Sachin S. Sapatnekar
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 1 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt