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ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
TVLSI
2008
150views more  TVLSI 2008»
13 years 3 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
HPCA
2009
IEEE
13 years 11 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
TIM
2010
294views Education» more  TIM 2010»
12 years 11 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 4 months ago
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit C...