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» Vectorless Analysis of Supply Noise Induced Delay Variation
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ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
10 years 8 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
IOLTS
2003
IEEE
133views Hardware» more  IOLTS 2003»
10 years 8 months ago
Power Consumption of Fault Tolerant Codes: the Active Elements
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
10 years 9 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
10 years 8 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
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