114 search results - page 1 / 23 » Verification by Simulation Comparison using Interface Synthe... |
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the res...
ANSS
2001
IEEE
13 years 8 months ago
2001
IEEE
BMVC
2002
13 years 7 months ago
2002
Statistical models of shape and appearance have been successfully used in face modeling, tracking and synthesis. In this paper we describe experiments using appearance models for ...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
BMCBI
2010
13 years 4 months ago
2010
Background: Meta-analysis methods exist for combining multiple microarray datasets. However, there are a wide range of issues associated with microarray meta-analysis and a limite...