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» Verification of Timed Systems Using POSETs
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FORMATS
2004
Springer
13 years 9 months ago
Modeling and Verification of a Fault-Tolerant Real-Time Startup Protocol Using Calendar Automata
We discuss the modeling and verification of real-time systems using the SAL model checker. A new modeling framework based on event calendars enables dense timed systems to be descr...
Bruno Dutertre, Maria Sorea
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 5 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
HASE
2008
IEEE
13 years 5 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
CAV
1994
Springer
111views Hardware» more  CAV 1994»
13 years 9 months ago
Automatic Verification of Timed Circuits
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
Tomas Rokicki, Chris J. Myers
ICLP
2009
Springer
14 years 6 months ago
Integrating Software Testing and Run-Time Checking in an Assertion Verification Framework
Abstract. We present a framework that unifies unit testing and runtime verification (as well as static verification and static debugging). A key contribution of our overall approac...
Edison Mera, Manuel V. Hermenegildo, Pedro L&oacut...