20 search results - page 1 / 4 » Verification of a CAN bus model in SystemC with functional c... |
SIES
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which...
FDL
2005
IEEE
13 years 10 months ago
2005
IEEE
Verification and validation are key issues for today's SoC design projects. This paper presents the implementation of a SystemC based environment for transaction-based verifi...
CORR
2007
Springer
13 years 4 months ago
2007
Springer
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequat...
CODES
2007
IEEE
13 years 8 months ago
2007
IEEE
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...