138 search results - page 4 / 28 » Very Compact FPGA Implementation of the AES Algorithm |
GLVLSI
2009
IEEE
2009
IEEE
Physical unclonable function and true random number generator: a compact and scalable implementation
13 years 9 months ago
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
ERSA
2009
13 years 3 months ago
2009
Abstract-- The paper presents the implementation of nonlinear least-squares regression in a Field Programmable Gate Array (FPGA) device. The implemented algorithm is very performan...
FSE
2005
Springer
13 years 11 months ago
2005
Springer
So far, efficient algorithmic countermeasures to secure the AES algorithm against (first-order) differential side-channel attacks have been very expensive to implement. In this a...
DDECS
2007
IEEE
14 years 8 days ago
2007
IEEE
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
CVIU
2010
13 years 6 months ago
2010
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...