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» Visibility enhancement for silicon debug
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DAC
2006
ACM
10 years 5 months ago
Visibility enhancement for silicon debug
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require ...
Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai...
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
10 years 6 months ago
Trace signal selection for visibility enhancement in post-silicon validation
Today’s complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from presilicon verification. One effective silicon debug ...
Xiao Liu, Qiang Xu
ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
10 years 8 months ago
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug
Abstract— This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradig...
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
DFT
2008
IEEE
86views VLSI» more  DFT 2008»
10 years 6 months ago
Enhancing Silicon Debug via Periodic Monitoring
Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is ti...
Joon-Sung Yang, Nur A. Touba
ATS
2010
IEEE
253views Hardware» more  ATS 2010»
9 years 9 months ago
On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and o...
Xiao Liu, Qiang Xu
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