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RTAS
2008
IEEE
13 years 11 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
RTSS
2008
IEEE
13 years 11 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut