2 search results - page 1 / 1 » Why area might reduce power in nanoscale CMOS |
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
ISQED
2007
IEEE
13 years 10 months ago
2007
IEEE
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...