2 search results - page 1 / 1 » Wire Planning with Bounded Over-the-Block Wires |
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...