18 search results - page 2 / 4 » Wiring layer assignments with consistent stage delays |
ISPD
2009
ACM
14 years 16 days ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
DAC
1999
ACM
13 years 10 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
ICPP
2007
IEEE
14 years 1 days ago
2007
IEEE
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
ISPD
1999
ACM
13 years 10 months ago
1999
ACM
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
ICC
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper concerns the cross-layer design between physical layer and MAC (Multiple Access Control) layer in asynchronous wireless random access network. The proposed cross-layer d...