12 search results - page 1 / 3 » Worst-case circuit delay taking into account power supply va... |
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
ICCAD
2003
IEEE
13 years 9 months ago
2003
IEEE
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
ISLPED
1996
ACM
13 years 8 months ago
1996
ACM
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...