12 search results - page 3 / 3 » Worst-case circuit delay taking into account power supply va... |
IOLTS
2003
IEEE
13 years 9 months ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
13 years 8 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....