85 search results - page 2 / 17 » Wrong-path Instruction Prefetching |
IEEEPACT
2000
IEEE
13 years 10 months ago
2000
IEEE
A multiprocessor prefetch scheme is described in which a miss is followed by a prefetch of a group of lines, a neighborhood, surrounding the demand-fetched line. The neighborhood ...
ASPLOS
2011
ACM
12 years 9 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
ISPDC
2010
IEEE
13 years 4 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...