19 search results - page 4 / 4 » Yield Estimation of VLSI Circuits with Downscaled Layouts |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
DAC
2004
ACM
13 years 9 months ago
2004
ACM
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a ...