Sciweavers

16 search results - page 2 / 4
» apcsac 2005
Sort
View
APCSAC
2005
IEEE
13 years 11 months ago
Targeted Data Prefetching
Abstract. Given the increasing gap between processors and memory, prefetching data into cache becomes an important strategy for preventing the processor from being starved of data....
Weng-Fai Wong
APCSAC
2005
IEEE
13 years 11 months ago
A Stream Architecture Supporting Multiple Stream Execution Models
Multimedia devices demands a platform integrated various functional modules and an increasing support of multiple standards. Stream architecture is able to solve the problem. Howev...
Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang
APCSAC
2005
IEEE
13 years 11 months ago
Speculative Issue Logic
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
You-Jan Tsai, Jong-Jiann Shieh
APCSAC
2005
IEEE
13 years 11 months ago
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
Shu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkum...
APCSAC
2005
IEEE
13 years 11 months ago
Energy-Effective Instruction Fetch Unit for Wide Issue Processors
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such ...
Juan L. Aragón, Alexander V. Veidenbaum