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ARITH
2003
IEEE
13 years 10 months ago
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II
Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2m ) which has a low hardware complexity and a low latenc...
Soonhak Kwon
ARITH
2003
IEEE
13 years 10 months ago
Decimal Floating-Point: Algorism for Computers
Decimal arithmetic is the norm in human calculations, and human-centric applications must use a decimal floating-point arithmetic to achieve the same results. Initial benchmarks i...
Michael F. Cowlishaw
ARITH
2003
IEEE
13 years 10 months ago
Revisiting SRT Quotient Digit Selection
The quotient digit selection in the SRT division algorithm is based on a few most significant bits of the remainder and divisor, where the remainder is usually represented in a r...
Peter Kornerup
ARITH
2003
IEEE
13 years 10 months ago
The Case for a Redundant Format in Floating Point Arithmetic
This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic opera...
Hossam A. H. Fahmy, Michael J. Flynn
ARITH
2003
IEEE
13 years 10 months ago
A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm
This paper presents a new approach to hardware division—the parallel paths algorithm. In this approach, prescaling allows the division recurrence to be implemented by three proc...
Eric Rice, Richard Hughey