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ARITH
2005
IEEE
13 years 11 months ago
Fast Modular Reduction for Large Wordlengths via One Linear and One Cyclic Convolution
Abstract— Modular reduction is a fundamental operation in cryptographic systems. Most well known modular reduction methods including Barrett’s and Montgomery’s algorithms lev...
Dhananjay S. Phatak, Tom Goff
ARITH
2005
IEEE
13 years 11 months ago
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
Javier D. Bruguera, Tomás Lang
ARITH
2005
IEEE
13 years 11 months ago
Table Lookup Structures for Multiplicative Inverses Modulo 2k
We introduce an inheritance property and related table lookup structures applicable to simplified evaluation of the modular operations “multiplicative inverse”, “discrete l...
David W. Matula, Alex Fit-Florea, Mitchell Aaron T...
ARITH
2005
IEEE
13 years 11 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
ARITH
2005
IEEE
13 years 7 months ago
Error-Free Computation of 8x8 2-D DCT and IDCT Using Two-Dimensional Algebraic Integer Quantization
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both 2-D Discrete Cosine Transform and Inverse DCT. The architecture uses a...
Khan Wahid, Vassil S. Dimitrov, Graham A. Jullien