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ARITH
2007
IEEE
14 years 3 days ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...
ARITH
2007
IEEE
14 years 3 days ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte
ARITH
2007
IEEE
14 years 3 days ago
Solving Constraints on the Intermediate Result of Decimal Floating-Point Operations
The draft revision of the IEEE Standard for FloatingPoint Arithmetic (IEEE P754) includes a definition for decimal floating-point (FP) in addition to the widely used binary FP s...
Merav Aharoni, Ron Maharik, Abraham Ziv
ARITH
2007
IEEE
14 years 3 days ago
Worst Cases of a Periodic Function for Large Arguments
One considers the problem of finding hard to round cases of a periodic function for large floating-point inputs, more precisely when the function cannot be efficiently approxim...
Guillaume Hanrot, Vincent Lefèvre, Damien S...
ARITH
2007
IEEE
14 years 3 days ago
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
Libo Huang, Li Shen, Kui Dai, Zhiying Wang