Sciweavers

8 search results - page 2 / 2
» arvlsi 1997
Sort
View
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
13 years 9 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
ARVLSI
1999
IEEE
162views VLSI» more  ARVLSI 1999»
13 years 10 months ago
Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip
The ability of animals to select a limited region of sensory space for scrutiny is an important factor in dealing with cluttered or complex sensory environments. Such an attention...
Timothy K. Horiuchi, Ernst Niebur
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
13 years 10 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick