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ASAP
2008
IEEE
119views Hardware» more  ASAP 2008»
13 years 6 months ago
An FPGA architecture for CABAC decoding in manycore systems
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arith...
Roberto R. Osorio, Javier D. Bruguera
ASAP
2000
IEEE
90views Hardware» more  ASAP 2000»
13 years 8 months ago
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures
MicroSIMD architectures incorporating subword parallelism are very efficient for application-specific media processors as well as for fast multimedia information processing in gen...
Ruby B. Lee
ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
13 years 8 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
13 years 8 months ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 8 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy