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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 7 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
13 years 11 months ago
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards
This paper proposes different low-cost coprocessors for public key authentication on 8-bit smart cards. Elliptic curve cryptography is used for its efficiency per bit of key and ...
Guerric Meurice de Dormale, Renaud Ambroise, David...
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
13 years 11 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
ASAP
2006
IEEE
142views Hardware» more  ASAP 2006»
13 years 7 months ago
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm
In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Us...
Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kus...
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
13 years 9 months ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee