Sciweavers

    11 search results - page 1 / 3
    » aspdac 2011
    Sort
    View
    ASPDAC
    2011
    ACM
    173views Hardware» more  ASPDAC 2011»
    Device-parameter estimation with on-chip variation sensors considering random variability
    12 years 8 months ago
    Device-parameter estimation with on-chip variation sensors considering random variability
    Download  www.tauworkshop.com
    Kenichi Shinkai, Masanori Hashimoto
    claim paper
    Read More »
    ASPDAC
    2011
    ACM
    183views Hardware» more  ASPDAC 2011»
    Multi-core parallel simulation of System-level Description Languages
    12 years 8 months ago
    Multi-core parallel simulation of System-level Description Languages
    Download  www.aspdac.com
    Rainer Dömer, Weiwei Chen, Xu Han, Andreas Ge...
    claim paper
    Read More »
    ASPDAC
    2011
    ACM
    172views Hardware» more  ASPDAC 2011»
    Managing complexity in design debugging with sequential abstraction and refinement
    12 years 8 months ago
    Managing complexity in design debugging with sequential abstraction and refinement
    Download  www.aspdac.com
    al Abstraction and Refinement Brian Keng and Andreas Veneris University of Toronto ASPASP--DAC 2011DAC 2011
    Brian Keng, Andreas G. Veneris
    claim paper
    Read More »
    ASPDAC
    2011
    ACM
    215views Hardware» more  ASPDAC 2011»
    An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
    12 years 8 months ago
    An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
    Download  www.kameyama.ecei.tohoku.ac.jp
    —This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
    Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...
    claim paper
    Read More »
    ASPDAC
    2011
    ACM
    227views Hardware» more  ASPDAC 2011»
    Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph
    12 years 8 months ago
    Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph
    Download  peace.snu.ac.kr
    – This paper concerns throughput-constrained parallel execution of synchronous data flow graphs. This paper assumes static mapping and dynamic scheduling of nodes, which has seve...
    Tae-ho Shin, Hyunok Oh, Soonhoi Ha
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.