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ASYNC
2002
IEEE
90views Hardware» more  ASYNC 2002»
13 years 10 months ago
An Event Spacing Experiment
Events in self-timed rings can propagate evenly spaced or as bursts. By studying these phenomena, we obtain a better understanding of the underlying dynamics of self-timed pipelin...
Mark R. Greenstreet, Anthony Winstanley, Aurelien ...
ASYNC
2002
IEEE
112views Hardware» more  ASYNC 2002»
13 years 10 months ago
A Negative-Overhead, Self-Timed Pipeline
This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagat...
Mark R. Greenstreet, Brian D. Winters
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
13 years 10 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
ASYNC
2002
IEEE
150views Hardware» more  ASYNC 2002»
13 years 10 months ago
Clock Synchronization through Handshake Signalling
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not...
Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters,...
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
13 years 10 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...