As integrated circuit technologies get smaller, circuit and architectural trends make transmitting data across long on-chip wires increasingly important yet increasingly expensive...
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
I use asynchronous FIFO stages that are connected in rings to generate and deliver highly precise timing signals. I introduce a Micropipeline FIFO control stage that oscillates at...