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ATVA
2004
Springer
13 years 10 months ago
2004
Springer
We propose a novel approach to locate errors in complex counterexample of safety property. Our approach measures the distance between two state transition traces with difference o...
ATVA
2004
Springer
13 years 10 months ago
2004
Springer
Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Te...
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
ATVA
2004
Springer
13 years 10 months ago
2004
Springer
Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino Department of Information Networking, ...