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CHARME
2001
Springer
162views Hardware» more  CHARME 2001»
13 years 9 months ago
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
Kenneth L. McMillan
CHARME
2001
Springer
92views Hardware» more  CHARME 2001»
13 years 9 months ago
Induction-Oriented Formal Verification in Symmetric Interconnection Networks
The framework of this paper is the formal specification and proof of applications distributed on symmetric interconnection networks, e.g. the torus or the hypercube. The algorithms...
Eric Gascard, Laurence Pierre
CHARME
2001
Springer
73views Hardware» more  CHARME 2001»
13 years 10 months ago
A Framework for Microprocessor Correctness Statements
Abstract Most verifications of out-of-order microprocessors compare state-machine-based implementations and specifications, where the specification is based on the instruction-s...
Mark Aagaard, Byron Cook, Nancy A. Day, Robert B. ...
CHARME
2001
Springer
105views Hardware» more  CHARME 2001»
13 years 10 months ago
Net Reductions for LTL Model-Checking
We present a set of reduction rules for LTL model-checking of 1-safe Petri nets. Our reduction techniques are of two kinds: (1) Linear programming techniques which are based on wel...
Javier Esparza, Claus Schröter
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
13 years 10 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft