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CHARME
2005
Springer
136views Hardware» more  CHARME 2005»
13 years 10 months ago
Predictive Reachability Using a Sample-Based Approach
Abstract. Unbounded model checking of invariant properties is typically solved using symbolic reachability. However, BDD based reachability methods suffer from lack of robustness ...
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer,...
CHARME
2005
Springer
136views Hardware» more  CHARME 2005»
13 years 10 months ago
Acceleration of SAT-Based Iterative Property Checking
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
Daniel Große, Rolf Drechsler
CHARME
2005
Springer
91views Hardware» more  CHARME 2005»
13 years 10 months ago
Temporal Modalities for Concisely Capturing Timing Diagrams
Timing diagrams are useful for capturing temporal specifications in which all mentioned events are required to occur. We first show that translating timing diagrams with both par...
Hana Chockler, Kathi Fisler
CHARME
2005
Springer
143views Hardware» more  CHARME 2005»
13 years 10 months ago
Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning
Abstract. We propose a new saturation-based symbolic state-space generation algorithm for finite discrete-state systems. Based on the structure of the high-level model specificat...
Gianfranco Ciardo, Andy Jinqing Yu
CHARME
2005
Springer
145views Hardware» more  CHARME 2005»
13 years 7 months ago
Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies
Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present sev...
Jason Baumgartner, Hari Mony