Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these ...
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work [3, 13] has established Elmore delay as a high delity estima...
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCo...
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...
Current asynchronous tools are focussed mainly on the design of a single interface module. In many applications, one must design interacting interface modules that potentially comm...