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DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
— The paper describes pre-integrated subsystem consisting of a configurable 8-bit microcontroller and an Internet connection solution. The latter integrates Ethernet Media Access...