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DFT
2000
IEEE
105views VLSI» more  DFT 2000»
13 years 9 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
DFT
2000
IEEE
119views VLSI» more  DFT 2000»
13 years 9 months ago
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications
1 Over the last years, an increasing number of safety-critical tasks have been demanded to computer systems. In particular, safety-critical computer-based applications are hitting ...
Maurizio Rebaudengo, Matteo Sonza Reorda, Marco To...
DFT
2000
IEEE
106views VLSI» more  DFT 2000»
13 years 9 months ago
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications
We present a configuration technique for a Large Area Integrated Circuit (LAIC) which is manufactured by wafer stepping. A LAIC consists of four identical subsystems, i.e., a subs...
Markus Rudack, Michael Redeker, Dieter Treytnar, O...
JCAMD
2010
65views more  JCAMD 2010»
13 years 3 months ago
Analysis of SM8 and Zap TK calculations and their geometric sensitivity
Abstract A prospective study of aqueous solvation energies was done using the SM8 and Zap TK models for a variety of geometries. CM4M charges calculated with M06 and M06-2X were fo...
Benjamin A. Ellingson, A. Geoffrey Skillman, Antho...
DATE
2000
IEEE
87views Hardware» more  DATE 2000»
13 years 9 months ago
Test Synthesis for Mixed-Signal SOC Paths
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu