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JCC
2006
70views more  JCC 2006»
9 years 1 months ago
SG-0: A small standard grid for DFT quadrature on large systems
: We report the development of a new standard quadrature grid for DFT calculations. Standard Grid 0 (SG-0) is designed to be approximately half as large as, and to provide approxim...
Siu-Hung Chien, Peter M. W. Gill
JMM2
2006
133views more  JMM2 2006»
9 years 1 months ago
An Adaptive Method for Image Recovery in the DFT Domain
In image authentication research, a common approach is to divide a given image into a number of smaller blocks, and embed a fragile watermark into each block. The modifications can...
Peining Tao, Ahmet M. Eskicioglu
ETS
2006
IEEE
106views Hardware» more  ETS 2006»
9 years 7 months ago
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete ...
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, ...
FPGA
2006
ACM
139views FPGA» more  FPGA 2006»
9 years 5 months ago
Fast and accurate resource estimation of automatically generated custom DFT IP cores
This paper presents an equation-based resource utilization model for automatically generated discrete Fourier transform (DFT) soft core IPs. The parameterized DFT IP generator all...
Peter A. Milder, Mohammad Ahmad, James C. Hoe, Mar...
ETS
2006
IEEE
108views Hardware» more  ETS 2006»
9 years 7 months ago
A DFT Architecture for Asynchronous Networks-on-Chip
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
Xuan-Tu Tran, Jean Durupt, François Bertran...
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