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DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done ...
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we propose an approach to the reduction of sizes of Multi-Terminal Binary Decision Diagrams (MTBDDs) [3] by using the copy properties of discrete functions. The und...
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the po...