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DSD
2003
IEEE
109views Hardware» more  DSD 2003»
13 years 10 months ago
A methodology for the design of AHB bus master wrappers
This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters. The AMBA AHB protocol is used as a case study in thi...
Marc Bertola, Guy Bois
DSD
2003
IEEE
108views Hardware» more  DSD 2003»
13 years 10 months ago
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique
This paper presents a method with an evolutionary approach to some of the tasks of integrated-circuit (IC) design. The work is focused on application-specific integrated circuits ...
Gregor Papa, Jurij Silc
DSD
2003
IEEE
97views Hardware» more  DSD 2003»
13 years 10 months ago
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
Ahmet Akkas, Michael J. Schulte
DSD
2003
IEEE
142views Hardware» more  DSD 2003»
13 years 10 months ago
FC-Min: A Fast Multi-Output Boolean Minimizer
We present a novel heuristic algorithm for two-level Boolean minimization. In contrast to the other approaches, the proposed method firstly finds the coverage of the on-sets and f...
Petr Fiser, Jan Hlavicka, Hana Kubatova
DSD
2003
IEEE
106views Hardware» more  DSD 2003»
13 years 10 months ago
Analytical Bounds on the Threads in IXP1200 Network Processor
Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] ...
S. T. G. S. Ramakrishna, H. S. Jamadagni