This paper describes principles of a novel two-level multi-output Boolean minimizer FC-Min, namely its Find Coverage phase. The problem of Boolean minimization is approached in a ...
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
Recently ultra-wideband (UWB) communications has emerged as an alternative to narrowband communications used in wireless sensor networks. One of UWB(s) most attractive feature for...
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...