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DSD
2004
IEEE
126views Hardware» more  DSD 2004»
13 years 9 months ago
Boolean Minimizer FC-Min: Coverage Finding Process
This paper describes principles of a novel two-level multi-output Boolean minimizer FC-Min, namely its Find Coverage phase. The problem of Boolean minimization is approached in a ...
Petr Fiser, Hana Kubatova
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
13 years 9 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
DSD
2004
IEEE
136views Hardware» more  DSD 2004»
13 years 9 months ago
FPGA Based Design of the Railway's Interlocking Equipments
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
Radek Dobias, Hana Kubatova
DSD
2004
IEEE
136views Hardware» more  DSD 2004»
13 years 9 months ago
Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation Scheme
Recently ultra-wideband (UWB) communications has emerged as an alternative to narrowband communications used in wireless sensor networks. One of UWB(s) most attractive feature for...
Matthew D'Souza, Adam Postula
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
13 years 9 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...