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DSD
2010
IEEE
140views Hardware» more  DSD 2010»
13 years 5 months ago
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
—Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtract...
Levent Aksoy, Eduardo Costa, Paulo F. Flores, Jos&...
DSD
2010
IEEE
133views Hardware» more  DSD 2010»
13 years 2 months ago
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
Igor Lemberski, Petr Fiser
DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 5 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
DSD
2010
IEEE
99views Hardware» more  DSD 2010»
13 years 5 months ago
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies
—Several alternatives of mesh-type topologies have been published for the use in Networks-on-Chip. Due to their regularity, mesh-type topologies often serve as a foundation to in...
Claas Cornelius, Philipp Gorski, Stephan Kubisch, ...
DSD
2010
IEEE
153views Hardware» more  DSD 2010»
13 years 5 months ago
Simulation of High-Performance Memory Allocators
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
José Luis Risco-Martín, José ...