334 search results - page 2 / 67 » eXtended Block Cache |
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
Recently-proposed architectures that continuously operate on atomic blocks of instructions (also called chunks) can boost the programmability and performance of shared-memory mult...
ASPLOS
2006
ACM
13 years 10 months ago
2006
ACM
For transactional memory (TM) to achieve widespread acceptance, transactions should not be limited to the physical resources of any specific hardware implementation. TM systems s...
CAL
2010
13 years 1 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
HIPEAC
2009
Springer
13 years 8 months ago
2009
Springer
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...