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MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
11 years 5 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by speciļ¬c assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
CGO
2004
IEEE
11 years 5 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
ASPLOS
2010
ACM
11 years 4 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
IMC
2010
ACM
10 years 11 months ago
Comparing DNS resolvers in the wild
The Domain Name System (DNS) is a fundamental building block of the Internet. Today, the performance of more and more applications depend not only on the responsiveness of DNS, bu...
Bernhard Ager, Wolfgang Mühlbauer, Georgios S...
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