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    ERSA
    2009
    131views Hardware» more  ERSA 2009»
    Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
    13 years 2 months ago
    Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
    Download  www.kameyama.ecei.tohoku.ac.jp
    An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
    Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
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    ERSA
    2009
    147views Hardware» more  ERSA 2009»
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    13 years 2 months ago
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    Download  eecs.wsu.edu
    Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
    Kylan Robinson, José G. Delgado-Frias
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    ERSA
    2009
    129views Hardware» more  ERSA 2009»
    Data path Configuration Time Reduction for Run-time Reconfigurable Systems
    13 years 2 months ago
    Data path Configuration Time Reduction for Run-time Reconfigurable Systems
    Download  ce.et.tudelft.nl
    - The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
    Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
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    ERSA
    2009
    146views Hardware» more  ERSA 2009»
    Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
    13 years 2 months ago
    Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
    Download  www.dcs.gla.ac.uk
    We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
    Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...
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    ERSA
    2009
    107views Hardware» more  ERSA 2009»
    Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
    13 years 2 months ago
    Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
    Download  eprints.eemcs.utwente.nl
    For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
    Kenneth C. Rovers, Marcel D. van de Burgwal, Jan K...
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