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EUROMICRO
1998
IEEE
13 years 9 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
EUROMICRO
1998
IEEE
13 years 9 months ago
Experiments with MHEG Player/Studio: An Interactive Hypermedia Visualization and Authoring System
With the growing needs of information sharing and exchange, MHEG-6(Multimedia Hypermedia information coding Expert Group - part 6) standard is defined so as to provide the interna...
Seungtaek Oh, Yung Yi, Seunghoon Jeong, Yanghee Ch...
EUROMICRO
1998
IEEE
13 years 9 months ago
Data Speculative Multithreaded Architecture
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
Pedro Marcuello, Antonio González
EUROMICRO
1998
IEEE
13 years 9 months ago
The Latency Hiding Effectiveness of Decoupled Access/Execute Processors
Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that w...
Joan-Manuel Parcerisa, Antonio González
EUROMICRO
1998
IEEE
13 years 9 months ago
Image Compression Using the Wavelet Transform on Textural Regions of Interest
This paper suggests a new image compression scheme, using the discrete wavelet transformation (DWT), which is based on attempting to preserve the texturally important image charac...
Dimitris A. Karras, S. A. Karkanis, Basil G. Mertz...