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FCCM
2008
IEEE
99views VLSI» more  FCCM 2008»
13 years 10 months ago
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs
We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx’s Virtex-5 FPGAs. An iterative “basic” module outputs a 32 bit col...
Saar Drimer, Tim Güneysu, Christof Paar
FCCM
2008
IEEE
177views VLSI» more  FCCM 2008»
13 years 10 months ago
Hardware Scripting in Gel
—Gel is a hardware description language that enables quick scripting of high level designs and can be easily extended to new design patterns. It is expression oriented and extrem...
Jonathan Bachrach, Dany Qumsiyeh, Mark Tobenkin
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
13 years 10 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
FCCM
2008
IEEE
115views VLSI» more  FCCM 2008»
13 years 10 months ago
Simultaneous Retiming and Placement for Pipelined Netlists
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...
Kenneth Eguro, Scott Hauck
FCCM
2008
IEEE
118views VLSI» more  FCCM 2008»
13 years 10 months ago
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
François Charot, Christophe Wolinski, Nicol...