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FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
13 years 10 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
ICES
2005
Springer
195views Hardware» more  ICES 2005»
13 years 10 months ago
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs
A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on t...
Jan Korenek, Lukás Sekanina
FPL
2005
Springer
136views Hardware» more  FPL 2005»
13 years 10 months ago
Architecture-Adaptive Routability-Driven Placement for FPGAs
Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates ...
Akshay Sharma, Carl Ebeling, Scott Hauck
FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
13 years 10 months ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
13 years 10 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose